The present invention relates to a program-controlled information processor having a simplified interruption control circuit.
When a program interruption request is issued during the execution of an instruction stream, it is necessary to interrupt the program to allow the execution of the interruption request.
The operation of the program-controlled processor is controlled by a program status word (PSW) which contains control information such as an address of an instruction to be executed next. Thus, when the interruption request is issued, the old PSW is buffered to a storage unit and a new PSW for the interruption execution program is used. After the completion of the interruption processing program, the old PSW is fetched to continue the execution of the instruction. When the interruption request is issued, the instruction address in the old PSW is modified to an address of the instruction to be executed after the completion of the interruption processing program, before the old PSW is buffered to the main storage. The instruction address of the old PSW must be determined depending on a type of interruption and the type of instruction. The type of interruption is determined depending on the process of the interrupted instruction and the instruction to be executed after the execution of the interruption processing program. Three typical examples thereof are explained below.
For a suppression type interruption, the instruction is not at all executed. For a completion type interruption, the execution of the instruction is completed. For a termination type interruption, the instruction is not executed after the interruption has occurred. That is, the suppression type interruption suppresses the initiation of the execution of the instruction, the completion type interruption suppresses the execution of the next sequential instruction and the termination type instruction carries out either one of the above processes depending on a particular machine.
When the interruption request is issued during the execution of an instruction other than a branch instruction, the instruction to be executed after the interruption processing program is the next sequential instruction of the interrupted instruction. Accordingly, the address of the next sequential instruction of the interrupted instruction has to be stored in the old PSW.
When the interruption request is issued during the execution of a branch instruction and if the interruption is of suppression type or termination type, the instruction to be executed after the interruption processing program is the next sequential instruction of the branch instruction (that is, an instruction in a branch failure stream). If the interruption is of completion type, the instruction to be executed after the interruption processing program is determined depending on whether the branch succeeds or fails as a result of the execution of the branch instruction. Thus, the instruction to be executed after the interruption processing program is the address of the next sequential instruction of the branch instruction when the interruption is of the suppression type or termination type, and when the interruption is of the completion type, it is the address of the instruction determined by the result of the branch (that is, the address of the next sequential instruction of the branch instruction when branch fails, and the branch-to instruction address when the branch succeeds). Accordingly, when the interruption request is issued during the execution of a branch instruction, the instruction address to be stored in the old PSW depends on the type of interruption and whether the branch succeeds or fails.
It should be further noted that one of the factors for the interruption is a program event recording (PER). When the program is interrupted due to the PER, a process for buffering the address of the interrupted instruction (called a PER address) to the storage unit is required in addition to the process described above. Usually, in order to determine the address of the interrupted instruction, the address of the next sequential instruction of the interrupted instruction and the instruction length of the interrupted instruction are detected. The address of the interrupted instruction is determined by subtracting the last-mentioned instruction length from the address of the next sequential instruction of the interrupted instruction to determine the address of the interrupted instruction. Accordingly, when the program interruption due to the PER is requested during the execution of the program other than a branch instruction, it is necessary to hold the address of the executed instruction for the PER address and the address to be stored in the old PSW. When the program interruption due to the PER is requested during the execution of a branch instruction, it is necessary to hold the address determined by the result of the branch (that is the address of the next sequential instruction of the branch instruction when the branch fails and the branch-to address when the branch succeeds) and the address of the next sequential instruction of the branch instruction, for the address to be stored in the old PSW and the PER address. When the program interruption due to the PER is requested after the branch has succeeded, it is necessary to hold both the branch-to address and the address of the next sequential instruction of the branch instruction. Thus, when the interruption is requested, various addresses have to be generated depending on the type of interruption and the type of interrupted instruction.
In a large-scale program-controlled information processing system, the instructions are usually executed in a plurality of stages and different stages of different instruction streams are executed in parallel. That is, the instructions are pipeline-processed.
Referring to FIG. 1, an instruction unit (I unit) 1 decodes an instruction to be executed and carries out a stage (D stage) for calculating addresses of operands necessary for the execution of the instruction. A storage control unit (S unit) 3 carries out a stage (A stage) for translating the operand addresses to addresses for accessing a main storage (MS) 4, and a stage (L stage) for fetching the operands from the main storage 4 and presenting them to an execution unit (E unit) 2. The E unit 2 carries out a stage (execution stage or E stage) for processing the instruction codes supplied from the I unit 1 and the operands supplied from the storage control unit 3, and a stage (S stage) for storing the processed results to the storage control unit 3. For each of the instructions, the stages D-S are sequentially carried out, and when each of the units completes the process of the given stage for one instruction, it immediately processes the same stage for the next sequential instruction.
In this manner, the instructions are executed in a plurality of stages and different stages of different instruction streams are carried out in parallel. When the interruption is requested during the execution of one instruction, that instruction terminates the execution of the next sequential stage of the next sequential instruction. In this case, various instruction addresses have to be generated depending on the type of interruption and the type of instruction, as discussed above.
Accordingly, when the I unit 1 decodes an instruction other than a branch instruction, it generates an address of the next sequential instruction of that instruction and holds that address until immediately before the initiation of the E stage of that instruction, when it supplies the address to the E unit 2. The E unit 2 stores the address and when the interruption request is detected during the execution of the E stage it reads out the stored instruction address during the execution of the interruption processing program to generate the address for the old PSW or the PER address.
On the other hand, when the I unit 1 decodes a branch instruction, the address of the next sequential instruction of the branch instruction (the instruction address in the branch failure stream) and the branch-to address (the instruction address in the branch success stream) are generated and held, and supplied to the E unit 2 immediately before the start of the E stage of the branch instruction. The E unit 2 stores those addresses and when the interruption request is issued, either one of those addresses is read as the address for the old PSW and the address of the next sequential instruction of the branch instruction is read as the instruction address for the PER.
Accordingly, two address lines are required to send the two instruction addresses from the I unit 1 to the E unit 2. While only the addresses have been discussed so far, not only the address of the instruction to be executed next but also the instruction length of the interrupted instruction are to be stored in the old PSW. Therefore, the two address lines as well as one instruction length code line are actually required. In a usual large-scale computer, the address comprises 24 bits and the instruction length code comprises two bits. Accordingly, total of at least 50 lines are required. Thus, the prior art system needs a number of lines connecting the I unit and the E unit and hence it is expensive. Furthermore, the prior art system has the following disadvantage.
As the operation speed of the circuit has become faster and faster in recent years, the time period occupied by one stage of each instruction, i.e., a machine cycle, has been shortened. However, as the machine cycle is more and more shortened, when the interruption request is issued in one stage of one instruction, it is impossible to terminate the execution of the next sequential stage of that instruction or the next sequential instruction of that instruction, and the instruction which should be terminated is executed. This is hereinafter called instruction overrun.
In order to resolve the above problem, the U.S. patent application Ser. No. 10,470, filed Feb. 8, 1979 which was assigned to the same assignee and corresponds to Japanese Published Unexamined Patent Application No. 54-107645 discloses a method for compensating the inconvenience due to the instruction overrun in the interruption processing program while permitting the instruction overrun. This method is hereinafter called an overrun method.
In the invention disclosed in the above-mentioned patent application, two addresses are sent from the I unit to the E unit through separate lines, and the instruction address control circuit holds those addresses in the registers in the E unit and shifts the contents of those registers to other registers as the stage proceeds. To this end, the instruction address control circuit is connected to the I unit through two address lines and it requires five registers and a circuit for controlling the data shift among those registers.
The above-mentioned patent application does not disclose the PER address generation circuit. As discussed above, in order to allow the interruption due to the PER, the instruction address control circuit has to be constructed to allow the generation of an address different from the instruction address for the old PSW when the interrupted instruction is a branch instruction and the branch has succeeded. When a plurality of registers are included and the contents thereof are to be shifted as taught in the above patent application, an additional register is required for the generation of the PER address and a complex shift control circuit therefor is required.